Clock Tree Synthesis(CTS)

Clock Tree Synthesis:
CTS:(requirement)

placement db
clock spec
(clock skew ,latency
max_transition
clock exceptions
max_capacitance
max_fanout
Buffers
Inverters
)Ndr

Constraints(period,false path ,multi cycle path)
to get optimized cts

minimize skew(can achieve by removing buffers in common path)

fanouts(do clonning,divide the fanouts .which can get better timing)

setup (by upsizing the cells ,or replace buffer by inverters ,reduce the wire length , these all can improve the timing ,can reduce the setup violation)

hold (by downsizing cells,add delay cells ,these all can reduce the hold violation by not getting the clock earlier)
The Buffers and inverters are added to reduce the delay and to balance the skew and the insertion delay.
There are different Clock tree structures. they are
1) H tree
2) X tree
3) cluster
4)fishbone 

The Htree is mostly preferred  because the tracks will be same for all the cells ,and can try to minimize  the skew.

Optimization is done to reduce the setup ,drv.

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