Sanity checks

Physical Design


1. Sanity Checks:
The inputs to the Physical design are checked here for


{The Sanity Checks to be done before floorplan
like 
Check Netlist for verifying the floating pins ,multidriven nets,tri state buffers,total std cells area,floating nets, fanout nets,

ReportConstarints -verbose
checks for Max transition,max fanout,max capacitance,setup,

checkDesign -timing library

in this total cells used ,missing timing for cells,don'tuse cells

checkDesign -physical library

in this we check for cells pins missing lef,cells missing geometry ,cells pins missing dimension,

}}}}
a) CheckNetlist: floating input, multidriven nets, black box, undriven Io’s, floating outputs, combinational loops
b) Check Timing checks like No_ideal_waveform, no drive, unconstraint_endpooints, no_input_drive. Checks for timing cells are also present in the physical lib.
c) CheckDesign –all: timing and netlist checks, and also check for tie hi and tie lo, max_fanout,
No.of Instances, total area, total io ports, high fan-out nets.


The timing checks are warnings, if there are any multidriven nets or floating inputs or any mismatch of timing library, we have to discuss with the manager or the top level

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