Onchip Variation


Onchip Variation and pvt
Process :which depends on the technology node(45nm ,90nm)which indicates
I =U cox W/L(vgs - vt)2 ,where L increase which affects the Drain current Id,
For The same Temperature and voltage values ,the current required for 45nm would be more than the current for 65nm
voltage :the voltage increase the delay decreases (faster the charging and Discharging)
The voltage may be drop or increase at some times ,so the design must work in that scenario.
Temperature : The climate changes can be -40 degrees and can be +50 degrees ,it have to work in between this conditions ,
HIgher the temperature ,the collision of electrons will me more ,the less electrons move and the less current,so the delay will be more.

Onchip Variation : The oxide and poly shape will not be straight line after etching ,it is irregular ,this may effect the drain current and capacitance ,where the delay will be increased or can be decreased due to change in the width of poly.
eg:
 if inverter of same size can have different delays due to their shape(due to etching)
delay is 100.
it can change -90 or -110 ,
so that the cell have to work for the both delay values.
this is on chip variation

Comments

Post a Comment

Popular posts from this blog

Checks done Before CTS

The checks to be done after placement 1)report_constraint -hotspot This command shows the top 5 highlighted area which are congested with representing the vertical and horizontal congestion.(local congestion) eg : V(31/28)  indicates three more vertical tracks are required in that area . 2)report_constraint -overflow This command indicates the total tracks vertical and  horizontal overflow e.g -1    0   0.00%   2 0.00% which indicates two tracks are less than the required 3)WNS,TNS 4)SLACK :If the slack is below - 200 ps ,The design can be routable ,make sure that the design is having less -ve slack. 5)Density : try to maintain at 75%(after placement) 6)max_transition : This can be reduced by adding clk_buffers  . max_capacitance : This can be balanced by using up-sizing of cells max_fanout :by doing clonning we can divide the fanout ,and can reduce the load. 7)checkPlace : this will do placement legalization of cells. (this will avoid overlap cells
Read more

Sanity checks

Physical Design 1. Sanity Checks : The inputs to the Physical design are checked here for {The Sanity Checks to be done before floorplan like  Check Netlist for verifying the floating pins ,multidriven nets,tri state buffers,total std cells area,floating nets, fanout nets, ReportConstarints -verbose checks for Max transition,max fanout,max capacitance,setup, checkDesign -timing library in this total cells used ,missing timing for cells,don'tuse cells checkDesign -physical library in this we check for cells pins missing lef,cells missing geometry ,cells pins missing dimension, }}}} a) CheckNetlist: floating input, multidriven nets, black box, undriven Io’s, floating outputs, combinational loops b) Check Timing checks like No_ideal_waveform, no drive, unconstraint_endpooints, no_input_drive. Checks for timing cells are also present in the physical lib. c) CheckDesign –all: timing and netlist checks, and also check for tie hi and
Read more